Design of a Low Power Fixed Width Replica Redundancy Block Based Multiplier

In this paper, we have a tendency to propose a reliable low-power number style by adopting recursive noise tolerant (ANT) design with the fixed-width number to make the reduced preciseness duplicate redundancy block (RPR). The planned hymenopteran design will meet the demand of high preciseness, low power consumption, and space potency. we have a tendency to style the fixed-width RPR with error compensation circuit via analyzing of chance and statistics. Victimization the partial product terms of input correction vector and minor input correction vector to lower the truncation errors, the hardware complexness of error compensation circuit may be simplified. in an exceedingly 12×12 bit hymenopteran number, circuit space in our fixed-width RPR may be down by forty four.55% and power consumption in our hymenopteran style may be saved by twenty third as compared with the state-of-art hymenopteran style.